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general description the max1473 fully integrated low-power cmos super- heterodyne receiver is ideal for receiving amplitude- shift-keyed (ask) data in the 300mhz to 450mhz frequency range. its signal range is from -114dbm to 0dbm. with few external components and a low-current power-down mode, it is ideal for cost- and power-sensi- tive applications typical in the automotive and consumer markets. the chip consists of a low-noise amplifier (lna), a fully differential image-rejection mixer, an on- chip phase-locked-loop (pll) with integrated voltage- controlled oscillator (vco), a 10.7mhz if limiting amplifier stage with received-signal-strength indicator (rssi), and analog baseband data-recovery circuitry. the max1473 also has a discrete one-step automatic gain control (agc) that drops the lna gain by 35db when the rf input signal is greater than -57dbm. the max1473 is available in 28-pin tssop and 32-pin thin qfn packages. both versions are specified for the extended (-40? to +85?) temperature range. applications automotive remote keyless entry security systems garage door openers home automation remote controls local telemetry wireless sensors systems features optimized for 315mhz or 433mhz ism band operates from single 3.3v or 5.0v supplies high dynamic range with on-chip agc selectable image-rejection center frequency selectable x64 or x32 f lo /f xtal ratio low 5.2ma operating supply current < 2.5 a low-current power-down mode for efficient power cycling 250 s startup time built-in 50db rf image rejection receive sensitivity of -114dbm max1473 315mhz/433mhz ask superheterodyne receiver with extended dynamic range ________________________________________________________________ maxim integrated products 1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 xtal2 pwrdn pdout dataout v dd5 dsp agcdis dffb opp dsn dfo ifin2 ifin1 xtalsel dvdd dgnd mixout irsel agnd mixin2 mixin1 avdd lnaout agnd lnasrc lnain avdd xtal1 tssop thin qfn top view max1473 32 31 30 29 28 27 26 lnasrc lnain avdd xtal1 xtal2 pwrdn pdout 25 n.c. 9 10 11 12 13 14 15 mixout dgnd dvdd agcdis n.c. xtalsel ifin1 16 ifin2 17 18 19 20 21 22 23 dfo dsn opp dffb n.c. dsp v dd5 8 7 6 5 4 3 2 irsel agnd mixin2 mixin1 avdd lnaout agnd max1473 1 n.c. 24 dataout + + part temp range pin-package max1473eui+ -40 c to +85 c 28 tssop max1473etj+ -40 c to +85 c 32 thin qfn-ep* pin configurations ordering information 19-2748; rev 5; 1/11 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. functional diagram and typical application circuit appear at end of data sheet. evaluation kit available + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad.
max1473 315mhz/433mhz ask superheterodyne receiver with extended dynamic range 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics (3.3v operation) ( typical application circuit , v dd = 3.0v to 3.6v, no rf signal applied, t a = -40? to +85?, unless otherwise noted. typical values are at v dd = 3.3v and t a = +25?.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd5 to agnd.......................................................-0.3v to +6.0v avdd to agnd .....................................................-0.3v to +4.0v dvdd to dgnd .....................................................-0.3v to +4.0v agnd to dgnd.....................................................-0.1v to +0.1v irsel, dataout, xtalsel, agcdis, pwrdn to agnd .....................................-0.3v to (v dd5 + 0.3v) all other pins to agnd ..............................-0.3v to (v dd + 0.3v) continuous power dissipation (t a = +70 c) 28-pin tssop (derate 12.8mw/? above +70?) .1025.6mw 32-pin thin qfn (derate 21.3mw/? above +70?).........................................................1702.1mw operating temperature ranges max1473e__ ..................................................-40? to +85? storage temperature range .............................-60? to +150? lead temperature (soldering 10s) ..................................+300? soldering temperature (reflow) .......................................+260? parameter symbol conditions min typ max units supply voltage v dd 3.3v nominal supply 3.0 3.3 3.6 v f rf = 315mhz 5.2 6.23 supply current i dd v p wrdn = v dd f rf = 433mhz 5.8 6.88 ma f rf = 315mhz 1.6 shutdown supply current i pwrdn v p wrdn = 0v, v xtalsel = 0v f rf = 433mhz 2.5 5.3 ? input voltage low v il 0.4 v input voltage high v ih v dd - 0.4 v input logic current high i ih 10 ? f rf = 433mhz, v irsel = v dd v dd - 0.4 f rf = 375mhz, v irsel = v dd /2 1.1 v dd - 1.5 image reject select (note 2) f rf = 315mhz, v irsel = 0v 0.4 v dataout voltage output low v ol 0.4 v dataout voltage output high v oh r l = 5k ? v dd - 0.4 v
max1473 315mhz/433mhz ask superheterodyne receiver with extended dynamic range _______________________________________________________________________________________ 3 dc electrical characteristics (5.0v operation) ( typical application circuit , v dd = 4.5v to 5.5v, no rf signal applied, t a = -40? to +85?, unless otherwise noted. typical values are at v dd = 5.0v and t a = +25?.) (note 1) parameter symbol conditions min typ max units supply voltage v dd 5.0v nominal supply 4.5 5.0 5.5 v f rf = 315mhz 5.2 6.04 supply current i dd v p wrdn = v dd f rf = 433mhz 5.7 6.76 ma f rf = 315mhz 2.3 shutdown supply current i pwrdn v p wrdn = 0v, v xtalsel = 0v f rf = 433mhz 2.8 6.2 ? input voltage low v il 0.4 v input voltage high v ih v dd - 0.4 v input logic current high i ih 10 ? f rf = 433mhz, v irsel = v dd v dd - 0.4 f rf = 375mhz, v irsel = v dd /2 1.1 v dd - 1.5 image reject select (note 2) f rf = 315mhz, v irsel = 0v 0.4 v dataout voltage output low v ol 0.4 v dataout voltage output high v oh r l = 5k v dd - 0.4 v ac electrical characteristics ( typical application circuit , v dd = 3.0v to 3.6v, all rf inputs are referenced to 50 , f rf = 315mhz, t a = -40? to +85?, unless otherwise noted. typical values are at v dd = 3.3v and t a = +25?.) (note 1). parameter symbol conditions min typ max units general characteristics startup time t on time for valid signal detection after v p wrdn = v oh 250 ? receiver input frequency f rf 300 450 mhz maximum receiver input level p rfin_max modulation depth > 18db 0 dbm average carrier power level -120 sensitivity (note 3) p rfin_min peak power level -114 dbm 8db agc hysteresis lna gain from low to high 150 ms lna in high-gain mode power gain 16 db f rf = 433mhz 1 - j3.4 f rf = 375mhz 1 - j3.9 input impedance z in_lna normalized to 50 (note 4) f rf = 315mhz 1 - j4.7 1db compression point p1db lna -22 dbm input-referred 3rd-order intercept iip3 lna -12 dbm
max1473 315mhz/433mhz ask superheterodyne receiver with extended dynamic range 4 _______________________________________________________________________________________ ac electrical characteristics (continued) ( typical application circuit , v dd = 3.0v to 3.6v, all rf inputs are referenced to 50 , f rf = 315mhz, t a = -40? to +85?, unless otherwise noted. typical values are at v dd = 3.3v and t a = +25?.) (note 1) parameter symbol conditions min typ max units lo signal feedthrough to antenna -80 dbm noise figure nf lna 2db lna in low-gain mode f rf = 433mhz 1 - j3.4 f rf = 375mhz 1 - j3.9 input impedance (note 4) z in_lna normalized to 50 f rf = 315mhz 1 - j4.7 1db compression point p1db lna -10 dbm input-referred 3rd-order intercept iip3 lna -7 dbm lo signal feedthrough to antenna -80 dbm noise figure nf lna 2db power gain 0db voltage gain reduction agc enabled (depends on tank q) 35 db mixer input-referred 3rd-order intercept iip3 mix -18 dbm output impedance z out_mix 330 noise figure nf mix 16 db f rf = 433mhz, v irsel = v dd 42 f rf = 375mhz, v irsel = v dd /2 44 image rejection (not including lna tank) f rf = 315mhz, v irsel = 0v 44 db conversion gain 330 if filter load 13 db intermediate frequency (if) input impedance z in_if 330 operating frequency f if bandpass response 10.7 mhz 3db bandwidth 20 mhz rssi linearity 0.5 db rssi dynamic range 80 db p rfin < -120dbm 1.15 rssi level p rfin > 0dbm, agc enabled 2.35 v rssi gain 14.2 mv/db lna gain from low to high 1.45 agc threshold lna gain from high to low 2.05 v
max1473 315mhz/433mhz ask superheterodyne receiver with extended dynamic range _______________________________________________________________________________________ 5 note 1: 100% tested at t a = +25 c. guaranteed by design and characterization over temperature. note 2: irsel is internally set to 375mhz ir mode. it can be left open when the 375mhz image rejection setting is desired. a 1nf capacitor is recommended in noisy environments. note 3: ber = 2 x 10 -3 , manchester encoded, data rate = 4kbps, if bandwidth = 280khz. note 4: input impedance is measured at the lnain pin. note that the impedance includes the 15nh inductive degeneration con- nected from the lna source to ground. the equivalent input circuit is 50 ? in series with 2.2pf. note 5: crystal oscillator frequency for other rf carrier frequency within the 300mhz to 450mhz range is (f rf - 10.7mhz)/64 for xtalsel = 0v, and (f rf - 10.7mhz)/32 for xtalsel = v dd . ac electrical characteristics (continued) ( typical application circuit , v dd = 3.0v to 3.6v, all rf inputs are referenced to 50 ? , f rf = 315mhz, t a = -40? to +85?, unless otherwise noted. typical values are at v dd = 3.3v and t a = +25?.) (note 1) parameter symbol conditions min typ max units data filter maximum bandwidth bw df 100 khz data slicer comparator bandwidth bw cmp 100 khz maximum load capacitance c load 10 pf output high voltage v dd5 v output low voltage 0v crystal oscillator v xtalsel = 0v 6.6128 f rf = 433mhz v xtalsel = v dd 13.2256 mhz v xtalsel = 0v 4.7547 crystal frequency (note 5) f xtal f rf = 315mhz v xtalsel = v dd 9.5094 mhz crystal tolerance 50 ppm input impedance from each pin to ground 6.2 pf
max1473 315mhz/433mhz ask superheterodyne receiver with extended dynamic range 6 _______________________________________________________________________________________ typical operating characteristics ( typical application circuit , v dd = 3.3v, f rf = 315mhz, t a = +25?, unless otherwise noted.) supply current vs. supply voltage max1473 toc01 supply voltage (v) supply current (ma) 3.5 3.4 3.3 3.2 3.1 5.0 5.1 5.2 5.3 5.4 5.5 5.6 4.9 3.0 3.6 +105 c +85 c +25 c -40 c supply current vs. rf frequency max1473 toc02 rf frequency (mhz) supply current (ma) 450 400 350 300 5.0 5.5 6.0 6.5 7.0 4.5 250 500 +105 c +25 c +85 c -40 c 100 0.01 -121 -118 -120 -119 -117 -116 -114 bit-error rate vs. average rf input power 0.1 1 10 max1473 toc03 average input power (dbm) bit-error rate (%) -115 f rf = 433mhz f rf = 315mhz sensitivity vs. temperature max1473 toc04 temperature ( c) sensitivity (dbm) 85 60 -15 10 35 -113 -112 -111 -110 -109 -108 -107 -106 -105 -114 -40 110 f rf = 315mhz f rf = 433mhz peak rf input power 1% ber if bandwidth = 280mhz rssi vs. rf input power max1473 toc05 rf input power (dbm) rssi (v) -20 -40 -60 -80 -100 -120 1.2 1.4 1.6 1.8 2.0 2.2 2.4 1.0 -140 0 if bandwidth = 280khz v agcdis = 0v v agcdis = v dd rssi and delta vs. if input power max1473 toc06 if input power (dbm) rssi (v) -10 -30 -50 -70 1.2 1.4 1.6 1.8 2.0 2.2 2.4 1.0 delta (db) -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 -3.5 -90 10 delta rssi system gain vs. frequency max1473 toc07 if frequency (mhz) system gain (db) 25 20 15 10 5 -20 -10 0 10 20 30 -30 030 upper sideband lower sideband from rfin to mixout f rf = 315mhz 50db image rejection image rejection vs. rf frequency max1473 toc08 rf frequency (mhz) image rejection (db) 430 380 330 35 40 45 50 55 30 280 480 f rf = 433mhz f rf = 375mhz f rf = 315mhz image rejection vs. temperature max1473 toc09 temperature ( c) image rejection (db) 60 35 10 -15 41 42 42 43 43 44 44 45 45 41 -40 85 f rf = 315mhz f rf = 375mhz f rf = 433mhz
max1473 315mhz/433mhz ask superheterodyne receiver with extended dynamic range _______________________________________________________________________________________ 7 5 -20 1 10 100 normalized if gain vs. if frequency -15 max1473 toc10 if frequency (mhz) normalized if gain (db) -10 -5 0 s11 magnitude-log plot of rfin max1473 toc11 rf frequency (mhz) magnitude (db) 901 802 604 703 208 307 406 505 109 -60 -50 -40 -30 -20 -10 0 10 20 30 -70 10 1000 315mhz -34db s11 smith plot of rfin max1473 toc12 600mhz 100mhz regulator voltage vs. regulator current max1473 toc13 regulator current (ma) regulator voltage (v) 35 25 15 2.6 2.7 2.8 2.9 3.0 3.1 2.5 545 +105 c +85 c -40 c +25 c v dd = 5.0v phase noise vs. offset frequency offset frequency (mhz) 1.e-05 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 phase noise (dbc/hz) 0 -140 -120 -100 -80 -60 -20 -40 max1473 toc14 f rf = 315mhz phase noise vs. offset frequency offset frequency (mhz) 1.e-05 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 phase noise (dbc/hz) 0 -140 -120 -100 -80 -60 -20 -40 max1473 toc15 f rf = 433mhz typical operating characteristics (continued) ( typical application circuit , v dd = 3.3v, f rf = 315mhz, t a = +25?, unless otherwise noted.)
max1473 315mhz/433mhz ask superheterodyne receiver with extended dynamic range 8 _______________________________________________________________________________________ pin description pin tssop tqfn name function 1 29 xtal1 1st crystal input. (see the phase-locked loop section.) 2, 7 4, 30 avdd positive analog supply voltage. for +5v operation, pin 2 is the output of an on-chip +3.2v low-dropout regulator and should be bypassed to agnd with a 0.1? capacitor as close as possible to the pin. pin 7 must be externally connected to the supply from pin 2 and bypassed to agnd with a 0.01? capacitor as close as possible to the pin (see the voltage regulator section and the typical application circuit ). 3 31 lnain low-noise amplifier input. (see the low-noise amplifier section.) 4 32 lnasrc low-noise amplifier source for external inductive degeneration. connect inductor to ground to set lna in p ut im p edance. ( see the low-noise am p lifier section. ) 5 2 agnd analog ground 6 3 lnaout low-noise amplifier output. connect to mixer through an lc tank filter. (see the low-noise am p lifier section. ) 8 5 mixin1 1st differential mixer input. connect through a 100pf capacitor to v dd3 side of the lc tank. 9 6 mixin2 2nd differential mixer input. connect through a 100pf capacitor to lc tank filter from lnaout. 10 7 agnd analog ground 11 8 irsel im ag e rej ecti on s el ect p i n. s et v i rs e l = 0v to center i m ag e r ej ecti on at 315m h z. leave irs e l unconnected to center i m ag e r ej ecti on at 375m h z. s et v irs e l = v d d to center i m ag e r ej ecti on at 433m h z. 12 9 mixout 330 mixer output. connect to the input of the 10.7mhz bandpass filter. 13 10 dgnd digital ground 14 11 dvdd positive digital supply voltage. connect to both of the avdd pins. bypass to dgnd with a 0.01? capacitor as close as possible to the pin (see the typical application circuit ). 15 12 agcdis agc control pin. pull high to disable agc. 16 14 xtalsel crystal divider ratio select pin. drive xtalsel low to select divider ratio of 64, or drive xtalsel high to select divider ratio of 32. 17 15 ifin1 1st differential intermediate frequency limiter amplifier input. decouple to agnd with a 1500pf capacitor. 18 16 ifin2 2nd differential intermediate frequency limiter amplifier input. connect to the output of a 10.7mhz bandpass filter. 19 17 dfo data filter output 20 18 dsn negative data slicer input 21 19 opp noninverting op-amp input for the sallen-key data filter 22 20 dffb data filter feedback node. input for the feedback of the sallen-key data filter. 23 22 dsp positive data slicer input 24 23 v dd5 +5v supply voltage. bypass to agnd with a 0.01? capacitor as close as possible to the pin. for +5v operation, v dd5 is the input to an on-chip voltage regulator whose +3.2v output appears at the pin 2 avdd pin. (see the voltage regulator section and the typical application circuit .) 25 24 dataout digital baseband data output 26 26 pdout peak detector output 27 27 pwrdn power-down select input. drive this pin with a logic high to power on the ic. 28 28 xtal2 2nd crystal input 1, 13, 21, 25 n.c. no connection ep exposed pad (tqfn only). connect ep to gnd.
max1473 315mhz/433mhz ask superheterodyne receiver with extended dynamic range _______________________________________________________________________________________ 9 detailed description the max1473 cmos superheterodyne receiver and a few external components provide the complete receive chain from the antenna to the digital output data. depending on signal power and component selection, data rates as high as 100kbps can be achieved. the max1473 is designed to receive binary ask data modulated in the 300mhz to 450mhz frequency range. ask modulation uses a difference in amplitude of the carrier to represent logic 0 and logic 1 data. voltage regulator for operation with a single +3.0v to +3.6v supply volt- age, connect avdd, dvdd, and v dd5 to the supply voltage. for operation with a single +4.5v to +5.5v supply voltage, connect v dd5 to the supply voltage. an on-chip voltage regulator drives one of the avdd pins to approximately +3.2v. for proper operation, dvdd and both the avdd pins must be connected together. bypass v dd5 , dvdd, and the pin 7 avdd pin to agnd with 0.01? capacitors, and the pin 2 avdd pin to agnd with a 0.1? capacitor, all placed as close as possible to the pins. low-noise amplifier the lna is an nmos cascode amplifier with off-chip inductive degeneration that achieves approximately 16db of power gain with a 2.0db noise figure and an iip3 of -12dbm. the gain and noise figure are depen- dent on both the antenna matching network at the lna input and the lc tank network between the lna output and the mixer inputs. the off-chip inductive degeneration is achieved by connecting an inductor from lnasrc to agnd. this inductor sets the real part of the input impedance at lnain, allowing for a more flexible input impedance match, such as a typical pcb trace antenna. a nominal value for this inductor with a 50 ? input impedance is 15nh, but is affected by pcb trace. see the typical operating characteristics for the relationship between the inductance and the lna input impedance. the agc circuit monitors the rssi output. when the rssi output reaches 2.05v, which corresponds to an rf input level of approximately -57dbm, the agc switches on the lna gain reduction resistor. the resis- tor reduces the lna gain by 35db, thereby reducing the rssi output by about 500mv. the lna resumes high-gain mode when the rssi level drops back below 1.45v (approximately -65dbm at rf input) for 150ms. the agc has a hysteresis of ~8db. with the agc func- tion, the max1473 can reliably produce an ask output for rf input levels up to 0dbm with a modulation depth of 18db. the lc tank filter connected to lnaout comprises l3 and c2 (see the typical application circuit ). select l3 and c2 to resonate at the desired rf input frequency. the resonant frequency is given by: where: l total = l3 + l parasitics c total = c2 + c parasitics l parasitics and c parasitics include inductance and capacitance of the pcb traces, package pins, mixer input impedance, lna output impedance, etc. these parasitics at high frequencies cannot be ignored, and can have a dramatic effect on the tank filter center fre- quency. lab experimentation should be done to opti- mize the center frequency of the tank. mixer a unique feature of the max1473 is the integrated image rejection of the mixer. this device eliminates the need for a costly front-end saw filter for most applica- tions. advantages of not using a saw filter are increased sensitivity, simplified antenna matching, less board space, and lower cost. the mixer cell is a pair of double balanced mixers that perform an iq downconversion of the rf input to the 10.7mhz if from a low-side injected lo (i.e., f lo = f rf - f if ). the image-rejection circuit then combines these signals to achieve a minimum 45db of image rejection over the full temperature range. low-side injection is required due to the on-chip image rejection architec- ture. the if output is driven by a source-follower biased to create a driving impedance of 330 ? ; this provides a good match to the off-chip 330 ? ceramic if filter. the voltage conversion gain is approximately 13db when the mixer is driving a 330 ? load. the irsel pin is a logic input that selects one of the three possible image-rejection frequencies. when v irsel = 0v, the image rejection is tuned to 315mhz. v irsel = v dd /2 tunes the image rejection to 375mhz, and when v irsel = v dd , the image rejection is tuned to 433mhz. the irsel pin is internally set to v dd /2 (image rejection at 375mhz) when it is left unconnected, there- by eliminating the need for an external v dd /2 voltage. f lc total total = 1 2
max1473 315mhz/433mhz ask superheterodyne receiver with extended dynamic range 10 ______________________________________________________________________________________ phase-locked loop the pll block contains a phase detector, charge pump/integrated loop filter, vco, asynchronous 64x clock divider, and crystal oscillator driver. besides the crystal, this pll does not require any external compo- nents. the vco generates a low-side local oscillator (lo). the relationship between the rf, if, and refer- ence frequencies is given by: f ref = (f rf - f if )/(32 m) where: m = 1 (v xtalsel = v dd ) or 2 (v xtalsel = 0v) to allow the smallest possible if bandwidth (for best sen- sitivity), the tolerance of the reference must be minimized. intermediate frequency/rssi the if section presents a differential 330 ? load to pro- vide matching for the off-chip ceramic filter. the six internal ac-coupled limiting amplifiers produce an overall gain of approximately 65db, with a bandpass fil- ter-type response centered near the 10.7mhz if fre- quency with a 3db bandwidth of approximately 11.5mhz. the rssi circuit demodulates the if by pro- ducing a dc output proportional to the log of the if sig- nal level, with a slope of approximately 14.2mv/db (see the typical operating characteristics ). the agc circuit monitors the rssi output. when the rssi output reaches 2.05v, which corresponds to an rf input level of approximately -57dbm, the agc switches on the lna gain reduction resistor. the resistor reduces the lna gain by 35db, thereby reducing the rssi out- put by about 500mv. the lna resumes high-gain mode when the rssi level drops back below 1.45v (approxi- mately -65dbm at rf input) for 150ms. the agc has a hysteresis of ~8db. with the agc function, the max1473 can reliably produce an ask output for rf input levels up to 0dbm with modulation depth of 18db. applications information crystal oscillator the xtal oscillator in the max1473 is designed to pre- sent a capacitance of approximately 3pf between the xtal1 and xtal2. if a crystal designed to oscillate with a different load capacitance is used, the crystal is pulled away from its stated operating frequency, intro- ducing an error in the reference frequency. crystals designed to operate with higher differential load capac- itance always pull the reference frequency higher. for example, a 4.7547mhz crystal designed to operate with a 10pf load capacitance oscillates at 4.7563mhz with the max1473, causing the receiver to be tuned to 315.1mhz rather than 315.0mhz, an error of about 100khz, or 320ppm. table 1. component values for typical application circuit component value for 433mhz rf value for 315mhz rf description c1 100pf 100pf 5% c2 2.7pf 4.7pf 0.1pf c3 100pf 100pf 5% c4 100pf 100pf 5% c5 1500pf 1500pf 10% c6 220pf 220pf 5% c7 470pf 470pf 5% c8 0.47? 0.47? 20% c9 220pf 220pf 10% c10 0.01? 0.01? 20% c11 0.01? 0.01? 20% c12 15pf 15pf depends on xtal c13 15pf 15pf depends on xtal l1 56nh 110nh toko ll1608-fh l2 15nh 15nh murata lqp11a l3 15nh 27nh murata lqp11a r1 5k ? 5k ? 5% x1 6.6128mhz or 13.2256mhz 4.7547mhz or 9.5094mhz x2 10.7mhz ceramic filter 10.7mhz ceramic filter murata sfecv10.7 series
max1473 315mhz/433mhz ask superheterodyne receiver with extended dynamic range ______________________________________________________________________________________ 11 in actuality, the oscillator pulls every crystal. the crys- tal? natural frequency is really below its specified fre- quency, but when loaded with the specified load capacitance, the crystal is pulled and oscillates at its specified frequency. this pulling is already accounted for in the specification of the load capacitance. additional pulling can be calculated if the electrical parameters of the crystal are known. the frequency pulling is given by: where: f p is the amount the crystal frequency pulled in ppm. c m is the motional capacitance of the crystal. c case is the case capacitance. c spec is the specified load capacitance. c load is the actual load capacitance. when the crystal is loaded as specified, i.e., c load = c spec , the frequency pulling equals zero. data filter the data filter is implemented as a 2nd-order lowpass sallen-key filter. the pole locations are set by the com- bination of two on-chip resistors and two external capacitors. adjusting the value of the external capaci- tors changes the corner frequency to optimize for dif- ferent data rates. the corner frequency should be set to approximately 1.5 times the fastest expected data rate from the transmitter. keeping the corner frequency near the data rate rejects any noise at higher frequen- cies, resulting in an increase in receiver sensitivity. the configuration shown in figure 1 can create a butterworth or bessel response. the butterworth filter offers a very flat amplitude response in the passband and a rolloff rate of 40db/decade for the two-pole filter. the bessel filter has a linear phase response, which works well for filtering digital data. to calculate the value of c5 and c6, use the following equations along with the coefficients in table 2: where f c is the desired 3db corner frequency. for example, choose a butterworth filter response with a corner frequency of 5khz: choosing standard capacitor values changes c5 to 470pf and c6 to 220pf, as shown in the typical application circuit . data slicer the purpose of the data slicer is to take the analog out- put of the data filter and convert it to a digital signal. this is achieved by using a comparator and comparing the analog input to a threshold voltage. one input is supplied by the data filter output. both comparator inputs are accessible off chip to allow for different methods of generating the slicing threshold, which is applied to the second comparator input. the suggested data slicer configuration uses a resistor (r1) connected between dsn and dsp with a capaci- tor (c4) from dsn to dgnd (figure 2). this configura- tion averages the analog output of the filter and sets the threshold to approximately 50% of that amplitude. with this configuration, the threshold automatically adjusts as the analog signal varies, minimizing the possibility for errors in the digital data. the sizes of r1 and c4 affect how fast the threshold tracks to the analog ampli- tude. be sure to keep the corner frequency of the rc circuit much lower than the lowest expected data rate. c k khz pf 5 1 000 1 414 100 3 14 5 450 . .. = ()( )()() ? c b akf c a kf c c 5 100 6 4 100 = ()()() = ()()() f c ccc c p m case load case spec = ? ? ? ? ? ? ? ? ++ 2 11 10 6 - rssi r df1 100k ? r df2 100k ? c5 19 dfo 21 opp 22 dffb c6 max1473 figure 1. sallen-key lowpass data filter table 2. coefficents to calculate c5 and c6 filter type a b butterworth (q = 0.707) 1.414 1.000 bessel (q = 0.577) 1.3617 0.618
max1473 315mhz/433mhz ask superheterodyne receiver with extended dynamic range 12 ______________________________________________________________________________________ note that a long string of zeros or 1? can cause the threshold to drift. this configuration works best if a cod- ing scheme, such as manchester coding, which has an equal number of zeros and 1?, is used. to prevent continuous toggling of dataout in the absence of an rf signal due to noise, hysteresis can be added to the data slicer as shown in figure 3. peak detector the peak detector output (pdout), in conjunction with an external rc filter, creates a dc output voltage equal to the peak value of the data signal. the resistor pro- vides a path for the capacitor to discharge, allowing the peak detector to dynamically follow peak changes of the data filter output voltage. for faster receiver startup, the circuit shown in figure 4 can be used. layout considerations a properly designed pcb is an essential part of any rf/microwave circuit. on high-frequency inputs and outputs, use controlled-impedance lines and keep them as short as possible to minimize losses and radia- tion. at high frequencies, trace lengths that are on the order of /10 or longer act as antennas. keeping the traces short also reduces parasitic induc- tance. generally, 1in of a pcb trace adds about 20nh of parasitic inductance. the parasitic inductance can have a dramatic effect on the effective inductance of a passive component. for example, a 0.5in trace con- necting a 100nh inductor adds an extra 10nh of induc- tance or 10%. to reduce the parasitic inductance, use wider traces and a solid ground or power plane below the signal traces. also, use low-inductance connections to ground on all gnd pins, and place decoupling capacitors close to all power-supply pins. chip information process: cmos data slicer r3 r1 r2 r4 25 dataout *optional 23 dsp 19 dfo 20 dsn c4 max1473 figure 3. generating data slicer hysteresis data slicer 25k ? 25 dataout 20 dsn 19 dfo 26 pdout 23 dsp max1473 47nf figure 4. using pdout for faster startup data slicer r1 25 dataout 20 dsn 19 dfo 23 dsp c4 max1473 figure 2. generating data slicer threshold
max1473 315mhz/433mhz ask superheterodyne receiver with extended dynamic range ______________________________________________________________________________________ 13 typical application circuit 28 c13 l1 c11 if v dd is 3.0v to 3.6v 4.5v to 5.5v then v dd3 is connected to v dd created by ldo, available at avdd (pin 2) c1 c2 l2 l3 c3 c4 v dd3 rf input v dd3 v dd c12 x1 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 max1473 dvdd if filter component values in table 1 x2 gnd in out dgnd mixout irsel agnd mixin2 mixin1 avdd lnaout c9 c10 agnd lnasrc lnain avdd xtal1 xtal2 to/from p power down data out pwrdn pdout dataout v dd5 dsp agcdis dffb c8 r1 r2 r3 c7 c6 c5 opp dsn dfo ifin2 ifin1 xtalsel c15 (see table) c14
max1473 315mhz/433mhz ask superheterodyne receiver with extended dynamic range 14 ______________________________________________________________________________________ functional diagram lnaout mixin1 mixin2 0? 90? ifin1 mixout ifin2 rssi r df2 100k ? r df1 100k ? divide by 64 vco loop filter phase detector crystal driver power down if limiting amps 14 lnasrc data slicer data filter q i automatic gain control image rejection 3.2v reg 24 2 irsel 13 5,10 avdd v dd5 dvdd dgnd agnd lnain 3 xtalsel 16 xtal1 1 xtal2 28 pwrdn 27 dataout 25 dsn 20 dsp 23 dfo 19 pdout 26 opp 21 dffb 22 4 15 6 8 9 11 12 17 18 agcdis 2 1 max1473 lna 7 avdd package type package code outline no. land pattern no. 28 tssop u28+1 21-0066 90-0171 32 thin qfn-ep t3255+3 21-0140 90-0001 package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing per - tains to the package regardless of rohs status.
max1473 315mhz/433mhz ask superheterodyne receiver with extended dynamic range maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 15 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 4 5/10 added lead-free parts and exposed pad in ordering information and pin description tables 1, 8 5 1/11 updated absolute maximum ratings , ac electrical characteristics , pin description , layout considerations , typical application circuit , functional diagram , and package information ; added voltage regulator section to the detailed description section 2, 3, 4, 8, 9, 12, 13, 14

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